
2004 Microchip Technology Inc.
DS30491C-page 257
PIC18F6585/8585/6680/8680
TABLE 19-2:
SUMMARY OF A/D REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111
PIR2
—
CMIF
—EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
-0-0 0000
PIE2
—
CMIE
—EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
-0-0 0000
IPR2
—
CMIP
—EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
-1-1 1111
ADRESH
A/D Result Register High Byte
xxxx xxxx
uuuu uuuu
ADRESL
A/D Result Register Low Byte
xxxx xxxx
uuuu uuuu
ADCON0
—
CHS3
CHS1
CHS0
GO/DONE
ADON
--00 0000
ADCON1
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0000
ADCON2
ADFM
—
ADCS2
ADCS1
ADCS0
0--- -000
PORTA
—
RA6
RA5
RA4
RA3
RA2
RA1
RA0
--xx xxxx
--uu uuuu
TRISA
—
PORTA Data Direction Register
--11 1111
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
xxxx xxxx
uuuu uuuu
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
xxxx xxxx
uuuu uuuu
TRISF
PORTF Data Direction Control Register
1111 1111
PORTH(1)
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
xxxx xxxx
uuuu uuuu
LATH(1)
LATH7
LATH6
LATH5
LATH4
LATH3
LATH2
LATH1
LATH0
xxxx xxxx
uuuu uuuu
TRISH(1)
PORTH Data Direction Control Register
1111 1111
Legend:
x
= unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note
1:
Only available on PIC18F8X8X devices.